View P4C1256L70SNILF_4225125.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 document # sram121 rev e revised june 2007 v cc current (commercial/industrial) ? operating: 70ma/85ma ? cmos standby: 100a/100a access times ?55/70 (commercial or industrial) single 5 volts 10% power supply easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs locations are specified on address pins a 0 to a 14 . read- ing is accomplished by device selection ( ce and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. package options for the p4c1256l include 28-pin 600 mil dip, 28-pin 300 mil cerdip, and 28-pin 300 mil nar- row body sop packages. p4c1256l low power 32k x 8 static cmos ram common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages ?28-pin 600 mil dip ?28-pin 300 mil cerdip ?28-pin 300 mil narrow body sop functional block diagram pin configuration description the p4c1256l device provides asynchronous opera- tion with matching access and cycle times. memory features the p4c1256l is a 262,144-bit low power cmos static ram organized as 32kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times of 55 ns and 70 ns are available. cmos is utilized to reduce power consumption to a low level. dip (p6, d5-2), sop (s11-3) top view
p4c1256l page 2 of 11 document # sram121 rev e recommended operating temperature & supply voltage maximum ratings (1) stresses greater than those listed can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to maximum ratings for extended periods can adversely affect device reliability. dc electrical characteristics (over recommended operating temperature & supply voltage) (2) temperature range (ambient) supply voltage 4.5v v cc 5.5v industrial (-40c to 85c) 4.5 v cc 5.5v commercial (0c to 70c) symbol parameter min max unit v cc supply voltage with respect to gnd -0.5 7.0 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 v cc + 0.5 v t a operating ambient temperature -55 125 c s tg -65 150 c i out output current into low outputs 25 ma i lat latch-up current >200 ma storage temperature symbol parameter v oh v ol v ih v il i li i lo i sb i sb1 output high voltage (i/o 0 - i/o 7 ) output low voltage (i/o 0 - i/o 7 ) input high voltage input low voltage v cc current cmos standby current (cmos input levels) v cc current ttl standby current (ttl input levels) output leakage current input leakage current i oh = ?1ma, v cc = 4.5v i ol = 2.1ma v cc = 5.5v, i out = 0 ma ce v cc -0.2v v cc = 5.5v, i out = 0 ma ce = v ih gnd v out v cc ind'l. ce v ih com'l. test conditions min max unit 2.4 2.2 -0.5 (3) -5 -2 -5 -2 v v v v a ma a 0.4 v cc + 0.3 0.8 +5 +2 3 100 +5 +2 a gnd v in v cc ind'l. com'l.
p4c1256l page 3 of 11 document # sram121 rev e symbol parameter test conditions max unit c in c out input capacitance output capacitance v in = 0v v out = 0v 7 9 pf pf symbol parameter -55 min max -70 min max unit t rc 55 ns t aa address access time 55 70 ns t ac chip enable access time 55 70 ns t oh output hold from address change 55 ns t lz chip enable to output in low z 55 ns t hz chip disable to output in high z 20 25 ns t oe output enable low to data valid 30 35 ns t olz output enable low to low z 55 ns t ohz output enable high to high z 20 25 ns t pu chip enable to power up time 00 ns t pd chip disable to power down time 55 70 ns read cycle time 70 capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0 mhz) ac electrical characteristics - read cycle (over recommended operating temperature & supply voltage) * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e. ce and we v il (max), oe is high. switching inputs are 0v and 3v. **as above but @ f=1 mhz and v il / v ih = 0v/ v cc . power dissipation characteristics vs. speed symbol parameter -55 -70 unit i cc dynamic operating current commercial industrial 70 85 70 85 15 25 15 25 ma ma -55 -70 temperature range * **
p4c1256l page 4 of 11 document # sram121 rev e timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce ce ce ce ce controlled) (5,7) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5)
p4c1256l page 5 of 11 document # sram121 rev e ac characteristics - write cycle (over recommended operating temperature & supply voltage) symbol parameter -55 max -70 max unit min min t wc t cw t as t wp t ah t dh t wz t ow write cycle time 55 70 ns chip enable time to end of write 50 60 ns address valid to end of write 50 60 ns address set-up time 00ns write pulse width 40 50 ns address hold time 00ns data valid to end of write 25 30 ns data hold time 0 0 ns write enable to output in high z 25 30 ns output active from end of write 55ns t aw t dw timing waveform of write cycle no. 1 ( we we we we we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the first transitioning address.
p4c1256l page 6 of 11 document # sram121 rev e 3ns write active read * including scope and test fixture. note: because of the high speed of the p4c1256l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.77v (thevenin voltage) at the comparator input, and a 589 ? resistor must be used in series with d out to match 639 ? (thevenin resistance). ac test conditions truth table input pulse levels input rise and fall times input timing reference level output timing reference level output load gnd to 3.0v 1.5v 1.5v see figures 1 and 2 mode standby standby d out disabled standby power i/o we we we we we oe oe oe oe oe ce ce ce ce ce high z high z d out high z x x h h l x x h l x h l l l standby active active high z x figure 1. output load figure 2. thievenin equivalent timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (10)
p4c1256l page 7 of 11 document # sram121 rev e data retention characteristics symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v max v cc = 2.0v 3.0v unit 10 15 600 900 v a ns ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. data retention waveform
p4c1256l page 8 of 11 document # sram121 rev e selection guide the p4c1256l is available in the following temperature, speed and package options. ordering information 55 70 plastic dip, 600 mil -55pc -70pc ceramic dip (cerdip) -55dc -70dc plastic soj, 300 mil -55snc -70snc industrial plastic dip, 600 mil -55pi -70pi ceramic dip (cerdip) -55di -70di plastic soj, 300 mil -55sni -70sni speed (ns) temperature range package commercial
p4c1256l page 9 of 11 document # sram121 rev e pkg # # pins symbol min max a 0.090 0.200 a1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 c 0.008 0.012 d 1.380 1.480 e1 0.485 0.550 e 0.600 0.625 e eb l 0.100 0.200 0 15 p6 28 (600 mil) 0.100 bsc 0.600 typ plastic dual in-line package pkg # # pins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d5-2 28 (300 mil) 0.300 bsc 0.100 bsc cerdip dual in-line package
p4c1256l page 10 of 11 document # sram121 rev e soic/sop small outline ic package pkg # # pins symbol min max a 0.094 0.110 a1 0.002 0.014 b 0.014 0.020 c 0.008 0.012 d 0.702 0.710 e e 0.291 0.300 h 0.463 0.477 h 0.010 0.029 l 0.020 0.042 0 8 s11-3 28 (300 mil) 0.050 bsc
p4c1256l page 11 of 11 document # sram121 rev e revisions document number : sram121 document title : p4c1256l low power 32k x 8 static cmos ram rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b jun-06 jdb added 28-pin ceramic dip c aug-06 jdb added lead free designation d mar-07 jdb corrected narrow sop width in ordering information and selection guide e jun-07 jdb corrected narrow sop package dimensions

▲Up To Search▲

Price & Availability of P4C1256L70SNILF

	To Download P4C1256L70SNILF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .